A typical integrated circuit includes an on-chip power distribution network that is configured to provide a specified supply voltage to circuit elements fabricated within the integrated circuit. Transient operating and loading conditions may cause certain endpoints of the distribution network to exhibit supply droop, whereby the endpoint provides a lower voltage than the specified voltage. A lower supply voltage may increase propagation delays of signals through the circuit elements. Conventional integrated circuits are designed to accommodate supply droop by including an additional voltage margin in the supply voltage to ensure that each circuit element operates according to a specified propagation delay when the voltage provided to the circuit element is within the voltage margin.
A given subsystem of circuit elements may be configured to perform certain operations within the integrated circuit. The subsystem may exhibit a certain propagation delay, which dictates a maximum operating speed for the subsystem. A typical integrated circuit includes a plurality of such subsystems, whereby the longest propagation delay among the plurality of subsystems defines the overall operating speed of the integrated circuit.
In many applications, operating the integrated circuit at a maximum system performance level within a constrained power budget is desirable. To achieve maximum system performance (i.e., minimizing the longest propagation delay), the voltage margin is set to a value that substantially guarantees an adequate supply voltage for operation at the maximum system performance level. A consequence of setting the voltage margin in this way is that system performance levels may be achieved at the expense of power efficiency.
Thus, there is a need for addressing this issue and/or other issues associated with the prior art.